The present disclosure relates generally to integrated circuits, such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to dynamic reconfiguration of logic implemented on integrated circuit (e.g., an FPGA).
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, field programmable gate arrays (FPGAs) are integrated circuits that are intended as relatively general-purpose devices. FPGAs may include logic that may be programmed (e.g., configured) after manufacturing to provide any desired functionality that the FPGA is designed to support. Thus, FPGAs contain programmable logic, or logic blocks, that may be configured to perform a variety of functions on the FPGAs, according to a designer's design. Additionally, FPGAs may include input/output (I/O) logic, as well as high-speed communication circuitry. For instance, the high-speed communication circuitry may support various communication protocols and may include high-speed transceiver channels through which the FPGA may transmit serial data to and/or receive serial data from circuitry that is external to the FPGA.
In ICs such as FPGAs, the programmable logic is typically configured using low level programming languages such as VHDL or Verilog. As these programs become more complex and/or sophisticated, the performance of the implementation on the integrated circuit may be negatively impacted. For example, ICs may include partial reconfiguration (PR) blocks, which enable reconfiguration of portions of the ICS logic via received bit streams. These bit streams have traditionally been provided via memory packets (e.g., memory PCIe Transaction Layer Packets (TLPs). Unfortunately, usage of memory packets has resulted in complex arbitration logic that directs application data and partial reconfiguration data. The complex arbitration logic may lead to implementation inefficiencies. Further, using PCIe transaction layer memory packet communications to provide the bit stream data may consume end point base address registers and make excessive memory allocations. Further, mechanisms for transaction layer memory packet communications may be fairly rigid, lacking customizability.